1/6 AN1263 application note may 2000 review of traditional bootstrap circuit: figure 1.0 depicts a typical six transistor, three phase dc-to-ac inverter bridge which uses the bootstrap method to power the floating gate drivers for the three upper power transistors. this bridge may employ either mosfets or igbts so in this text i will use the generic term, transistor, which applies to both. please note that the gate drivers for the three lower transistors are powered directly by the vcc power supply which is referred to signal common, which is the same circuit node as the negative side of the main dc supply bus and the source (or emitter) terminals of the lower transistors. since the gate must be driven high with respect to the source (emitter) of the transistor, the gate drivers for the upper transistors and their respective power supplies must be referenced to the nodes labeled va, vb, and vc, respectively and float up and down with these motor terminal voltages. consider the gate driver for transistor qah. the power supply for this driver is the stored charge in capacitor c1. when the control for this bridge is first powered-up, but before any transistors have been gated, gating sig- nals are applied to all three of the lower transistors for a time interval of about one or two milliseconds. during this pre-charge period, the negative terminals of c1, c2, and c3 are connected via a low impedance path to circuit common, which will cause current to flow through diodes d1, d2, and d3 until the bootstrap capacitors have been charged up to approximately the voltage level of vcc. whenever an upper transistor is turned on, its source (emitter) terminal will be pulled up nearly to the level of the plus side of the dc bus (which is normally higher than vcc) and the positive terminal of the bootstrap capacitor will fly up to the level of the dc bus plus vcc (the initial voltage it was charged up to). in this instance the bootstrap capacitor can be thought of like a dry cell battery that is free to float up and down with the motor terminal and continue to power the gate driver. unfortunately, unlike a battery which can contin- ually supply output current and maintain its output voltage, a capacitor will discharge, with its voltage decreasing in direct proportion to the time integral of the current it supplies. the discharging of the bootstrap capacitors is not normally a problem, however, because the current drawn by the gate driver is very small and the normal operation of the inverter bridge offers periodic opportunities to recharge the cap. if the inverter bridge is being used to power either an induction motor or a sinusoidally driven brushless dc mo- tor (also called permanent magnet synchronous), then the three individual phases ( qah & qal, qbh & qbl, and qch & qcl ) are each operated simultaneously in a complementary mode so as to produce a close approxima- tion of a three phase set of sinusoidal phase voltages, displaced from each other by 120 electrical degrees. consider phase a. transistor qah and qal are alternately gated, one gating signal being essentially the logic inverse of the other except for a short dead time of one or two microseconds at the transition from upper on to lower on or vice versa when both are left off. during the latter or off part of each pulse width modulation cycle, qal is gated, which pulls va to ground and provides a low impedance dc path to recharge the bootstrap capac- itor. by: dennis nolan using the internal bootstrap charge capability of the l6384, 85, and 86 in driving a six transistor inverter bridge
AN1263 application note 2/6 another gating scheme commonly used with this bridge is the so-called six step commutation method. six step commutation is used primarily with brushless dc motors which employ three hall effect sensors to provide rotor position information which is used to control commutation. with six step commutation, no more than two of the six transistors are active at any one time. these transistor pairs consist of one upper and one lower transistor and are referred to as phases ab, ac, bc, ba, ca, and cb. the first letter indicates which one of the upper transistors is on while the second indicates the lower. note that with six step commutation one of the three mo- tor wires is always de-energized, with no current flowing in it. pulse width modulation is most often accom- plished by leaving the upper transistor on during the entire sixty degree interval for the given phase and modulating the lower one, or leaving the lower one on and modulating the upper, or sometimes modulating both on and off together. consider phase ab, modulating the lower transistor. during the on part of the pwm cycle, va is pulled up to the dc bus, vb is pulled down to ground, c2 is being charged and c1 has lost charge equal to the required gate charge of qah and continues to be discharged by the quiescent current requirements of the qah gate driver plus whatever leakage currents flow in the transistor gate circuit and on the circuit board itself. during the off part of the pwm cycle, va is still pulled up to the dc bus and vb is also pulled up to the dc bus since the motor current that was flowing down through qbl is now freewheeling up through the diode associated with qbh. none of the bootstrap capacitors charge during this interval. if the motor should get stuck on this phase, either because the motor is stalled by an excessive load or it is being used in a positioning type application and being com- manded to hold position (perhaps against a gravity load as would be common in a robotics type application), then the charge on c1 will eventually be depleted to the point where operation of the bridge cannot continue. many integrated gate drivers monitor the bootstrap capacitor voltage and will shutdown when it falls below a preset threshold. we should note here that if the motor does move on to the next phase ( which would be ac in normal abc rotation sequencing), c3 will get charged but poor c1 will still get none. the next phase, which is bc, will be of no help to our starving capacitor either, but if we can keep the motor moving into the next phase, ba, then c1 will finally get its much needed refresh charge. now let us consider phase ab, modulating the upper transistor. the on part of the pwm cycle is, of course, the same situation as that described previously for bottom modulation. during the off part of the pwm cycle, vb is still pulled down to ground and va is also pulled down to ground since the motor current that was flowing down through qah is now freewheeling up through the diode associated with qal. both bootstrap capacitors c1 and c2 will charge during this interval. as long as the off time of the pwm is adequately long, and we should not need much time since the impedance in the charging circuit is low, this situation can be sustained indefinitely and we can loiter on any given phase for as long as we wish. it is for this reason that modulation of the upper transistor has been generally preferred when the bootstrap method is used. bootstrap circuit using the stmicroelectronics l6384, 5, and 6: now let us consider specifically usage of the stmicroelectronics l6384, l6385, and l6386 integrated gate driv- ers. these chips contain one gate driver which is referred to ground and one floating gate driver. three of these chips would be used to operate a six transistor inverter bridge. an examination of the block diagram given in the data sheet for one of these parts will show that a major advance has been made in the design of these parts compared to previous floating driver designs since the external high voltage, fast recovery, diode is no longer required for charging the bootstrap capacitor. there are some caveats which must be observed when using these parts compared to the traditional approach using an external diode. these differences stem from the fact that, although the integrated charging circuit is referred to as a bootstrap diode and is drawn as such in the block diagram, this circuit is actually realized by a diode in series with a mosfet transistor switch which is gat- ed synchronously with the lower gate driver. this diode/mosfet combination can be accurately modeled by
3/6 AN1263 application note one of the two circuits presented in figure 3. circuit one, which consists of an ideal (no forward drop) diode in series with a 0.7vdc independent voltage source and a 125 ohm resistor, is valid whenever the lower driver in on. circuit two, the same circuit except that the voltage source is now 3.2vdc, is valid whenever the lower driv- er is off. figure 2 shows the new circuit with the diodes replaced by a diode/mosfet series circuit. for the most part, the synchronously gated mosfet operates very similarly to a diode in this circuit, but there can arise some subtle differences which must be considered. in the case of sinusoidal commutation, where the upper and lower transistors of each phase are alternately gat- ed in a nearly complimentary (except for dead time) manner, the bootstrap caps get depleted during the on part of the pwm period for each independent phase, but then get recharged during the off part, when the lower tran- sistor is on (providing a charging path to ground) and the charging mosfet is on (providing a charging path from vcc). some attention should be paid to the sizing of the bootstrap capacitor so that the time constant formed between the cap and the 125 ohms rdson of the charging mosfet is not too large compared to the pwm off time. this will not normally present a problem, however, since the charge accumulated during the off part of the pwm cycle will probably be more than the charge lost during the on part of the cycle. now consider six step, phase ab again. whether upper or lower modulation is employed, the main concern here is that while we are on phase ab, for example, the lower gate driver for phase a is never turned on and thus the mosfet which charges c1 is never turned on. a secondary effect causes the mosfet to behave like a conventional source follower circuit and this accounts for the additional 2.5 volts of drop shown in the equivalent circuit (the 2.5 volts is the effective gate threshold voltage of the mosfet). if the motor loiters for too long a time without changing phase, then c1 will decay to vcc-3.2vdc, which may cause the upper driver to shut down due to undervoltage in the bootstrap cap, depending on the value of vcc. while the traditional bootstrap circuit (external diode) favors upper modulation, lower modulation is preferred when using the l6384, 5, or 6. this is because modulating the upper transistor removes charge from the bootstrap cap with every pwm cycle since the transistor gate charge is removed from the cap every time the transistor is turned on. with lower modulation, the situation with the upper driver is static and we have only leakage currents discharging the cap. this situation forestalls the eventual shutdown, it does not eliminate it. one possible modification of the six step gating scheme steals from synchronous rectification methodology. if we employ the conventional top modulation six step gating scheme we know that, if we are on phase ab for example, during the off part of the pwm cycle current will be freewheeling up through the diode associated with qal. there is no reason why we cannot go ahead and turn on qal during this interval. the mosfet is just as happy operating in the third quadrant (reverse voltage and reverse current) as in the first, and the voltage drop across the device will actually be lower giving rise to lower device power dissipation ( ala synchronous rectifi- cation). an igbt will not conduct in the third quadrant but it wont hurt anything to gate it. of course, since the lower gate driver is on, the capacitor charging mosfet is on and c1 gets its refresh. we should mention here that a dead time must be allowed between turning off the upper and turning on the lower transistor or vice versa to allow for the turnoff time of the transistor. this will generally be just a few microseconds. peak bootstrap voltage may be lower compared to diode circuit : a final caveat. when we use six step commutation with upper modulation and the traditional bootstrap circuit (which employs the fast external diode), during charging the negative terminal of the capacitor is connected to the cathode of a freewheeling diode which is carrying heavy current. since the anode of this freewheeling diode is connected to ground, the cathode will normally be driven from 1.0 to 1.5 volts below ground. as long as heavy
AN1263 application note 4/6 current flows through the diode, this point can be thought of as a low impedance voltage source at -1.0 to -1.5 volts. the positive terminal of the cap connects to vcc via the fast recovery diode. this charging circuit has a total charging potential of vcc plus 1.0 to 1.5vdc available to charge the cap. some voltage will be lost across the diode, but current will be low at the end of the charging cycle, this drop will probably be only a few tenths of a volt. with the internal charging circuit method, whenever the cap is being charged the lower mosfet is on and current is flowing down through the device. this will bring the negative terminal of the bootstrap capacitor above ground to a voltage of rdson times the load current. this will probably get in the neighborhood of 0.5vdc or so. this give a total charging circuit potential of vcc minus 0.5vdc. the net effect of this difference could be a lower bootstrap capacitor voltage on the order of 1.0 to 2.0 volts. if vcc is 15vdc this is not likely to be a con- cern. if vcc is 12vdc or lower, it may pose a problem. if all else fails: a final note. any of these problems can be circumvented by putting an external diode around the part anyhow. the bootstrap circuit will then work pretty much in the traditional manner. figure 1. figure 2. 1 c1 qah 2 3 1 c2 qbh va vb vc d00in1112 2 3 1 c3 qch 2 1 qal 2 3 1 qbl 2 3 1 qcl 2 3 3 d1 dc vcc 2 d2 2 d3 2 1 c1 qah 2 3 1 c2 qbh va vb vc d00in1113 2 3 1 1 1 11 c3 qch 2 2 2 1 2 1 2 22 1 qal 2 3 1 qbl 2 3 1 qcl 2 3 3 d1 dc vcc 3 d2 3 d3 q1 q2 q3 3
5/6 AN1263 application note figure 3. equivalent circuit for internal b00tstrap charging path notes: the upper plot (channel 2) is the 1.5 m f bootstrap capacitor voltage at 2.0 volts per division. the zero reference for channel 2 is the bottom major graticule. the lower plot (channel 1) is the output voltage at 10.0 volts per division the zero reference for channel 1 is one major division up from the bottom. timebase is 2.0 milliseconds per division vbus is set at approximately 18vdc. vcc for the l6385 is set to precisely 14.0vdc. observations: in this configuration, the circuit alternates between two operating modes, a and b. in mode a, hin is gated at 25 khz and lin is held low. the plot shows the output voltage switching between groung and vbus while the bootstrap voltage decays. in mode b, hin is held low while lin is held high, allowing the bootstrap cap an op- portunity to charge up to within one volt of vcc. this alternate mode switching closely resembles the situation found in six step modulation. vcc vboot circuit one lower gate drive on circuit two lower gate drive off vboot ideal diode 0.7vdc 125 w (@t=25o) 125 w (@t=25o) 3.2vdc diode ideal vcc 12 12 d00in1114
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